吳江楓，1995年獲清華大學學士，2002年獲美國卡內基梅隆（Carnegie Mellon University）大學博士。2003年至2015年在美國博通公司工作。2016年起擔任六合彩結果-六合彩開獎號碼
教授。IEEE高級會員，現任IEEE CICC會議技術程序委員會成員和IEEE ICTA會議技術程序委員會成員。
主要研究方向為混合信號集成電路與通信芯片，是全頻段捕獲（Full-Band Capture）技術的創始人之一。擁有15項美國獲批專利，發表論文27篇，被引用過千次。近5年在IEEE JSSC，ISSCC，VLSI和CICC四個集成電路領域水平最高的期刊會議發表論文10篇。曾獲ADI杰出學生設計師獎，Broadcom CEO成就獎等。
研究方向：集成電路設計，通信芯片
代表論文：
1.Jiangfeng Wu, G. Cusmai, A. Wei-Te Chou, et al., “A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver”, IEEE Journal of Solid-State Circuits, Vol.51, No.4, 2016, pp.845 – 859.
2.Jiangfeng Wu, Acer Wei-Te Chou, Tianwei Li, et al., “A 4GS/s 13b Pipelined ADC with Capacitor and Amplifier Sharing in 16nm CMOS”, 2016 IEEE International Solid-State Circuits Conference (ISSCC), pp.466-467, February 1-4, 2016.
3.M. Brandolini, Jiangfeng Wu, et al., “A 5GS/s 150mW 10b SHA-Less Pipelined/SAR Hybrid ADC in 28nm CMOS”, IEEE Journal of Solid-State Circuits, Vol.50, No.12, 2015, pp.2922 – 2934.
4.Jiangfeng Wu, Chun-Ying Chen, et al., “A 240-mW 2.1-GS/s 52dB-SNDR Pipeline ADC Using MDAC Equalization”, IEEE Journal of Solid-State Circuits, Vol.48, No.8, 2013, pp.1818 – 1828.
5.Jiangfeng Wu, A. Wei-Te Chou, et al., “A 5.4GS/s 12b 500mW Pipeline ADC in 28nm CMOS”, 2013 Symposium on VLSI Circuits (VLSI), pp.92-93, June 12-14, 2013, Kyoto, Japan.
6.Chun-Ying Chen, Jiangfeng Wu, et al., “A 12-Bit 3 GS/s Pipeline ADC With 0.4mm2 and 500mW in 40nm Digital CMOS”, IEEE Journal of Solid-State Circuits, Vol.47, No.4, 2012, pp.1013 – 1021.
7.Jiangfeng Wu and L.R. Carley, “Electromechanical Delta-Sigma Modulation with High-Q Micromechanical Accelerometers and Pulse Density Modulated Force Feedback”, IEEE Transactions on Circuits and Systems I, Vol.53, No.2, Feb, 2006.
8.Jiangfeng Wu, G.K. Fedder and L.R. Carley, “A Low-Noise Low-Offset Capacitive Sensing Amplifier for a 50-?g/√Hz Monolithic CMOS MEMS Accelerometer”, IEEE Journal of Solid-State Circuits, Vol.39, No.5 , 2004, pp.722 – 730.
